This invention relates to a semiconductor memory device and more particularly to a semiconductor memory device including memory cells, in which a prescribed program is set, and thereafter data stored in the memory device is fixed by melting away a fuse link constituting a memory cell.
Recently, demand is rapidly increases for the development of a programmable read only memory (abbreviated as "PROM") which enables the user to provide a program freely and quickly. A known memory cell constituting PROM includes the type in which the p-n junction of a semiconductor element constituting a memory cell is purposely destroyed or a fuse link forming part of a memory cell is melted away. A memory cell whose fuse link is melted away is formed of a combination of a diode 10 and a fuse link 11 as shown in FIG. 1. Description is now given of a memory cell connected between a word line WL.sub.1 and bit line BL.sub.1. If data stored in a memory cell whose fuse link 11 is not melted away is logically expressed as "1" or "0", then data stored in a memory cell whose fuse link 11 is melted away is indicated by the reverse logic level of "0" or "1". Therefore, the user can freely provide a program for PROM. The fuse link 11 is melted away by conducting a sufficient amount of current through the word line WL.sub.1 and bit line BL.sub.1. The melting of the fuse link 11 constitutes a writing operation. The fuse link 11 is generally formed of a nichrome alloy or polycrystalline silicon layer.
FIG. 2 is a sectional view of a prior art diode memory cell having a fuse link. In FIG. 2, an n.sup.+ layer 13 is embedded in a p type semiconductor substrate 12. An n type layer 14 is epitaxially grown on the substrate 12. A plurality of p.sup.+ type partitioning regions 15 are formed to separate the respective memory cells from each other. An n.sup.+ type diffused region 16 and p type diffused region 17 are formed in the N type epitaxial layer 14 disposed between every adjacent partitioning regions 15. An aluminium electrode 19 is formed to connect through a contact hole provided in an insulation layer 18, the n.sup.+ type diffused region 16 and one end of the fuse link 11. Another aluminium electrode 20 constituting a word line WL.sub.1 is formed in contact with the p type diffused region 17 through a contact hole of the insulation layer 18. Still another aluminium electrode 21 constituting the bit line BL.sub.1 contacts the other end of the fuse 11. The diode 10 is formed of a p-n junction defined between the p type diffused region 17 and n type epitaxial layer 14.
With the memory cell of FIG. 2, a certain masking allowance should be taken when the partition region 15, p type diffused region 17 and n.sup.+ type diffused region 16 are formed in the n type epitaxial layer 14. It is further necessary to provide a sufficient space between the p.sup.+ type partitioning region 15 and p type diffused region 17, as well as between the p type diffused region 17 and n.sup.+ type diffused region 16 in order to elevate the breakdown voltage therebetween. Therefore, the diode region is increased in area, resulting in the failure to integrate the memory cells with the greater density. Further, a relatively large capacitance is sustained in a space defined between the p.sup.+ type partitioning region 15 and n type epitaxial layer 14 and also in the p-n junction of the diode 10, making it impossible to elevate the switching speed of the memory cell.